1. Field of the Invention
This invention relates to the field of debug controllers and more particularly to a process for speeding up the accessing of machine state information from a device under test using boundary scan circuitry technology.
2. Description of Related Art
It is a recurring problem in examining devices under test to have such tests conducted at a sufficiently rapid speed. This problem is particularly acute in accessing machine state information from a device under test (DUT) such as a very high speed integrated circuit (VHSIC) processor using boundary scan circuitry technology. The boundary scan circuitry, also called fault isolation test system (FITS), provides the user with access to all of the input/output of all the configurable gate arrays (CGAs) as well as the state of all their testable D flip flops (TDFFs). Current methods of accessing this information are too slow to be useful for debug functions.
In the general prior art methods, access to the boundary scan circuitry is provided by a Universal 1 Configured Gate Array (UNIV) in the boundary scan circuitry controller mode. In this mode, the UNIV can accept boundary scan circuitry commands and pass them on to the target CGA. The commands originate from an external controller, such as a personal computer or a DEC .mu.VAX. The external controller communicates with the boundary scan circuitry controller through test set and console interfaces. In a typical debug function, such as examining a register of a DUT, the external controller might have to use as many as 36 commands, each of which originate in the external controller. This expands into as many as a thousand sixteen-bit words being sent over the communication path.
FIG. 1 shows the steps necessary in the execution of a command in accordance with the current prior art methods. As shown in FIG. 1, external controller 10, such as a personal computer or microvax, generates the commands which are accepted by FITS controller 12 of VHSIC gate array processor 14 and ultimately passed on to the target CGA 16. External controller 10 communicates with FITS controller 12 through test set 18 and console 20. It is the serial communication path between external controller 10 and CGA 16, including the test set interface 22 and console interface 24, which is the primary cause for the slowness of the current prior art methods.
According to the command structure of FIG. 1, the execution of a prior art debug command is completely serial. A command cannot begin until the previous command is complete. This serial process means that many of the resources in the communication path between external controller 10 and CGA 16 such as console 20, FITS controller 12, plate funnel 26 and shop replaceable unit (SRU) funnel 28 are idle throughout the majority of operational time. Moreover, most of the data being sent back and forth between external controller 10 and CGA 16 is intermediary data. The transfer of such data creates a tremendous undesirable over-head.
Attempts have been made to improve the execution speed of boundary scan circuitry routines. Such efforts have focused on improving the interface 22 between the external controller 10 and test set 18 and the interface 24 between test set 18 and console 20. Improvements in these interfaces have provided a single order magnitude of improvement in speed for some projects. Nevertheless, as shown in FIG. 1, the time needed to access a single piece of machine state information may still take up to five seconds. Consequently, there is a need for an improved method of executing debug commands.